1. Field
Example embodiments may relate to a sense amplifier, for example, to a sense amplifier having a smaller area.
2. Description of the Related Art
FIG. 1A illustrates a related art open bit line structure having a connection of bit line pairs BL and /BL, sense amplifiers 111, and memory cells 101, 102, and 103. As shown in FIG. 1A, the bit line BL and the complementary bit line /BL may be included in different memory cells in related art open bit line structure. In a folded bit line structure (not shown), a bit line BL and a complementary bit line /BL may be arranged in parallel and may be included in the same memory cell. The sense amplifier 111 may sense a voltage difference between a bit line 121 and a complementary bit line 123 connected to the memory cells 101 and 102, respectively, arranged at both sides of the sense amplifier 111.
FIG. 1B illustrates a related art 6F2 (2F×3F) memory cell used in open bit line structure. Many memory cells used in the open bit line structure may have a 6F2 structure, while many memory cells used in the folded bit line structure may have an 8F2 structure.
As shown in FIG. 1B, the ratio of the horizontal size of the related art 6F2 memory cell to the vertical size may be about 3:2. A single related art memory cell may include a single MOS transistor 171 and/or a single capacitor 173. The vertical distance between a ground voltage source and a bit line BL may be referred to as 2F and the shortest distance between the capacitor 173 and a word line WL may be referred to as 3F. 6F2 may indicate that the area occupied by a single memory cell is 2F×3F. In the related art 8F2 structure, the horizontal and vertical distances of a memory cell may be respectively 4F and 2F, and the area occupied by a single memory cell may be 2F×4F.
The area of a bit line sense amplifier included in a related art memory device having a 6F2 memory cell may be dependent upon a front layer. A front layer may be the total layout area of an active region, a direct contact, and a gate poly of a MOS transistor. The area of the bit line sense amplifier may be dependent upon the active region of a MOS transistor, the distance between the direct contact and the gate poly of the MOS transistor, and/or the length of the direct contact. The active region may be a region in which holes and/or electrons may be heavily doped to form source and/or drain regions of a MOS transistor. In a PMOS transistor, source and/or drain regions may be doped with p+ impurities, and holes may form a channel. In an NMOS transistor, the active region may be doped with n+ impurities. The direct contact may be a node at which a voltage line (bit line) may be connected to the source, gate, or drain of a MOS transistor to apply a voltage to the source, gate, or drain.
A MOS transistor may be designed according to a design rule in order to perform a normal operation desired by a user. To prevent a short-circuit of the source and/or drain of the MOS transistor and generation of a parasitic capacitance, a specific rule may be specified. For example, the channel of the MOS transistor may not short-circuit if a distance between the gate and the source direct contact of the MOS transistor and a distance between the gate and the drain direct contact of the MOS transistor are maintained. The gate and the direct contacts may be arranged having substantially constant distances between them to satisfy the design rule.
The design rule may be variably applied to each MOS transistors. The design rule may be applied to a MOS transistor to be fabricated in consideration of the voltage, size, and layout structure of the MOS transistor. For example, an NMOS transistor that is about 2 μm in width and about 4 μm in length may be turned on by a 0.6V potential applied to its gate. If the channel of the NMOS transistor short-circuits when the distance between the gate and the drain direct contact departs from about 0.3 μm, a design rule that the distance between the gate and the drain direct contact be maintained greater than about 0.3 μm may be applied. Accordingly, the design rule may not be fixed and may vary with the conditions of a MOS transistor to which the design rule is applied.
The distance between a direct contact and the gate of a MOS transistor may be one of the elements determining the area of the front layer. The area of the front layer may be reduced by decreasing the distance between the direct contact and the gate.
FIG. 2 is a circuit diagram of a related art bit line sense amplifier 200. As shown in FIG. 2, the related art bit line sense amplifier 200 may include a sensing unit 210, an equalizer 230, and/or a sensing controller 250. The sensing unit 210 may sense a bit line pair including a bit line BL and/or a complementary bit line /BL. The sensing unit 210 may include a sensing NMOS transistor pair 216 and 218 and/or a PMOS sensing transistor pair 212 and 214.
The equalizer 230 may include a first equalization transistor 232 and/or a second equalization transistor 234 and may equalize the bit line pair BL and /BL in a period during which a sensing operation may not be performed. In the period during which the sensing operation may not be carried out, an equalization control signal PEQIJB at a logic high level may be applied to the first and second equalization transistors 232 and 234 to turn on the first and second equalization transistors 232 and 234. The bit line BL and the complementary bit line /BL may be electrically connected to each other and may have the same voltage.
The sensing controller 250 may include first, second, third, and/or fourth NMOS transistors 252, 254, 256, and 262 and may control the voltages of the bit line BL and the complementary bit line /BL before and after the bit line BL and the complementary bit line are sensed. If a wordline enabling signal WLE at a logic high level is applied to the bit line sense amplifier 200 to start the sensing operation, a first control signal LANG at a logic high level may be applied to turn on the fourth NMOS transistor 262. The voltage of a second node N2 may become a low power supply voltage V_SS. The voltage VBL of the bit line BL before the bit line BL is sensed may be applied to the gate of the second sensing NMOS transistor 218 of the sensing unit 210, and the second sensing NMOS transistor 218 may turn on. The voltage of the second node N2 may be applied to the complementary bit line /BL, and the voltage difference between the bit line BL and the complementary bit line /BL may increase.
Before the sensing operation, the first, second, and third NMOS transistors 252, 254, and 256 of the sensing controller 250 may be all turned on. First, second and third nodes N1, N2, and N3 may have the same voltage as the voltage VBL. Because the first and second equalization transistors 232 and 234 may be all tuned on before the sensing operation, the voltages of the bit line BL and the complementary bit line /BL may correspond to the voltage of the third node N3. Both the bit line BL and the complementary bit line /BL may have the voltage VBL.
The area of the bit line sense amplifier 200 may be determined by the front layer, as described above with reference to FIG. 1B. In the related art bit line sense amplifier 200, the equalizer 230 and the sensing unit 210 each may have active regions. The layout structure of the first and second NMOS transistors 216 and 218 of the sensing unit 210 and the first and second equalization transistors 232 and 234 of the equalizer 230 may include four gates, four source direct contacts, and/or four drain direct contacts. The distances between the direct contacts and the gates may be maintained greater than values according to the design rule. The area of the conventional bit line sense amplifier may increase.
It may be necessary to reduce the area of the conventional bit line sense amplifier by decreasing the number of gates included in the sense amplifier or changing the layout structure.